148 Inspection Items for PCB Design -PCB checklist

8. Confirm whether all device packages are consistent with the company's unified library and whether the package library has been updated (check the running results with viewlog). If they are not consistent, be sure to Update the Symbols
9. Confirm that the main board and the sub-board, as well as the single board and the backboard, have corresponding signals, positions, correct connector directions and silk-screened markings, and that the sub-board has anti-misinsertion measures. The components on the sub-board and the main board should not interfere
10. Whether the components are 100% placed
11. Open the place-bound of the TOP and BOTTOM layers of the device to check whether the DRC caused by the overlap is allowed
12. Mark whether the points are sufficient and necessary

For heavier components, they should be placed close to the PCB support points or support edges to reduce the warping of the PCB

After the components related to the structure are laid out, it is best to lock them to prevent accidental movement of positions

Within a 5mm radius around the crimping socket, there should be no components on the front that exceed the height of the crimping socket, and no components or solder joints on the back

16. Confirm whether the component layout meets the process requirements (with particular attention to BGA, PLCC, and surface mount sockets)

For components with metal casings, special attention should be paid to not colliding with other components, and sufficient space should be left

18. Interface-related devices should be placed as close as possible to the interface, and the backplane bus driver should be placed as close as possible to the backplane connector
19. Has the CHIP device with wave soldering surface been converted to wave soldering packaging?
20. Whether the number of manual solder joints exceeds 50

When installing taller components axially on a PCB, horizontal installation should be considered. Leave room for lying down. And consider the fixation method, such as the fixed pads of the crystal oscillator

22. For components that require heat sinks, ensure there is sufficient distance from other components and pay attention to the height of the main components within the range of the heat sink

23. When laying out the digital circuit and analog circuit devices on the digital-analog mixed board, have they been separated? Is the signal flow reasonable
24. The A/D converter is placed across analog-to-digital partitions.
25. Whether the layout of the clock devices is reasonable
26. Whether the layout of high-speed signal devices is reasonable
27. Whether the terminal devices have been placed reasonably (the source-end matching serial resistance should be placed at the driving end of the signal; The intermediate matching string resistance is placed in the middle position. Terminal matching serial resistance should be placed at the receiving end of the signal.
28. Whether the number and position of decoupling capacitors in IC devices are reasonable
29. When the signal lines take planes of different levels as reference planes and cross the plane division area, check whether the connection capacitors between the reference planes are close to the signal trace area.
30. Whether the layout of the protection circuit is reasonable and conducive to division
31. Is the fuse of the single-board power supply placed near the connector and there are no circuit components in front of it
32. Confirm that the circuits for strong signals and weak signals (with a power difference of 30dB) are laid out separately
33. Whether the devices that may affect the EMC test are placed in accordance with the design guidelines or by referring to successful experiences. For example: The reset circuit of the panel should be slightly close to the reset button

34. Heat-sensitive components (including liquid dielectric capacitors and crystal oscillators) should be kept as far away as possible from high-power components, heat sinks and other heat sources
35. Whether the layout meets the thermal design requirements and the heat dissipation channels (implemented according to the process design documents)

36. Is the IC power supply too far from the IC
37. Whether the layout of the LDO and the surrounding circuits is reasonable
38. Is the layout of the surrounding circuits such as the module power supply reasonable
39. Whether the overall layout of the power supply is reasonable

40. Have all the simulation constraints been correctly added to Constraint Manager
41. Whether the physical and electrical rules are correctly set (pay attention to the constraint Settings of the power network and the ground network)
42. Whether the spacing Settings of Test Via and Test Pin are sufficient
43. Whether the thickness and scheme of the laminated layer meet the design and processing requirements
44. Have the impedances of all differential lines with characteristic impedance requirements been calculated and controlled by rules

45. Have the traces of the digital circuit and the analog circuit been separated? Is the signal flow reasonable
46. If A/D, D/A and similar circuits divide the ground, do the signal lines between the circuits run from the bridge points between the two places (except for the differential lines)?
47. Signal lines that must cross the gaps between power sources should refer to the complete ground plane.
48. If the stratum design zoning without division is adopted, it is necessary to ensure that digital signals and analog signals are routed separately.

49. Whether the impedance of each layer of the high-speed signal line is consistent
50. Are high-speed differential signal lines and similar signal lines of equal length, symmetrical and parallel to each other?
51. Make sure the clock line moves as far inside as possible
52. Confirm whether the clock line, high-speed line, reset line and other strong radiation or sensitive lines have been laid out as much as possible in accordance with the 3W principle
53. Are there no forked test points on clocks, interrupts, reset signals, 100M/gigabit Ethernet, and high-speed signals?
54. Are low-level signals such as LVDS and TTL/CMOS signals satisfied as much as possible with 10H (H is the height of the signal line from the reference plane)?
55. Do the clock lines and high-speed signal lines avoid passing through dense through-hole and through-hole areas or routing between device pins?
56. Has the clock line met the (SI constraint) requirements? (Has the clock signal trace achieved fewer vias, shorter traces, and continuous reference planes? The main reference plane should be GND as much as possible?) If the GND main reference plane layer is changed during layering, is there a GND via within 200mil from the via? If the main reference plane of different levels is changed during layering, is there a decoupling capacitor within 200mil from the via?
57. Whether the differential pairs, high-speed signal lines, and various types of buses have met the (SI constraint) requirements

58. For the crystal oscillator, is a layer of ground laid beneath it? Has the signal line been avoided crossing between the device pins? For high-speed sensitive devices, is it possible to avoid signal lines passing through the pins of the devices?
59. There should be no sharp angles or right angles on the single-board signal path (generally, it should make continuous turns at a 135-degree Angle. For RF signal lines, it is best to use arc-shaped or calculated beveled copper foil).
60. For double-sided boards, check whether the high-speed signal lines are routed closely next to their return ground wires. For multi-layer boards, check whether the high-speed signal lines are routed as close to the ground plane as possible

For the adjacent two layers of signal traces, try to trace them vertically as much as possible

62. Avoid signal lines passing through power modules, common mode inductors, transformers, and filters
63. Try to avoid long-distance parallel routing of high-speed signals on the same layer
64. Are there any shielding vias at the edge of the board where the digital ground, analog ground and protected ground are divided? Are multiple ground planes connected by vias? Is the through-hole distance less than 1/20 of the wavelength of the highest frequency signal?
65. Is the signal trace corresponding to the surge suppression device short and thick on the surface layer?
66. Confirm that there are no isolated islands in the power supply and stratum, no overly large grooves, no long ground surface cracks caused by overly large or dense through-hole isolation plates, and no slender strips or narrow channels
67. Have ground vias (at least two ground planes are required) been placed in areas where signal lines cross more floors?

68. If the power/ground plane is divided, try to avoid the crossing of high-speed signals on the divided reference plane.
69. Confirm that the power supply and ground can carry sufficient current. Whether the number of vias meets the load-bearing requirements. (Estimation method: When the outer copper thickness is 1oz, the line width is 1A/mm; when the inner layer is 0.5A/mm, the current of the short line is doubled.)
70. For power supplies with special requirements, has the voltage drop requirement been met
71. To reduce the edge radiation effect of the plane, the 20-hour principle should be satisfied as much as possible between the power source layer and the stratum. If conditions permit, the more the power layer is indented, the better.
72. If there is a ground division, does the divided ground not form a loop?
73. Did the different power supply planes of adjacent layers avoid overlapping placement?
74. Is the isolation of the protective ground, -48V ground and GND greater than 2mm?
75. Is the -48V area only a -48V signal backflow and not connected to other areas? If it cannot be done, please explain the reason in the remarks column.
76. Is a protective ground of 10 to 20mm placed near the panel with the connector, and are the layers connected by double rows of interlaced holes?
77. Does the distance between the power line and other signal lines meet the safety regulations?

Under metal housing devices and heat dissipation devices, there should be no traces, copper sheets or vias that may cause short circuits

There should be no traces, copper sheets or through holes around the installation screws or washers that may cause short circuits

80. Is there any wiring at the reserved positions in the design requirements

The distance between the inner layer of the non-metallic hole and the circuit and copper foil should be greater than 0.5mm (20mil), and the outer layer should be 0.3mm (12mil). The distance between the inner layer of the shaft hole of the single-board pull-out wrench and the circuit and copper foil should be greater than 2mm (80mil).

82. The copper sheet and wire to the edge of the board are recommended to be more than 2mm and at least 0.5mm
83. The copper skin of the inner stratum is 1 to 2 mm from the edge of the plate, with a minimum of 0.5mm

For CHIP components (0805 and below packages) with two pad mounts, such as resistors and capacitors, the printed lines connected to the pad should preferably be symmetrically led out from the center of the pad, and the printed lines connected to the pad must have the same width. This regulation does not need to be considered for lead lines with a width less than 0.3mm(12mil)

85. For the pads connected to the wider printing line, is it best to pass through a narrow printing line in the middle? (0805 and below packages)
86. The circuits should be led out from both ends of the pads of devices such as SOIC, PLCC, QFP, and SOT as much as possible

87. Check if the device bit number is missing and if the position can correctly identify the device
88. Whether the device bit number complies with the company's standard requirements
89. Confirm the correctness of the pin arrangement sequence of the device, the marking of pin 1, the polarity marking of the device, and the direction marking of the connector
90. Whether the insertion direction markings of the master board and the sub-board correspond
91. Has the backplane correctly marked the slot name, slot number, port name and sheath direction
92. Confirm whether the silk-screen printing addition as required by the design is correct
93. Confirm that anti-static and RF board labels have been placed (for RF board use).

94. Confirm that the PCB code is correct and complies with the company's specifications
95. Confirm that the PCB code position and layer of the single board are correct (it should be in the upper left corner of the A side, the silk-screen layer).
96. Confirm that the PCB coding position and layer of the backplane are correct (it should be in the upper right corner of B, with the outer copper foil surface).
97. Confirm that there is a barcode laser printed white silk-screen marking area
98. Confirm that there are no wires or through holes larger than 0.5mm under the barcode frame
99. Confirm that within a 20mm range outside the white silk-screened area of the barcode, there should be no components with a height exceeding 25mm

100. On the reflow soldering surface, the vias cannot be designed on the pads. The distance between the normally opened via and the pad should be greater than 0.5mm (20mil), and the distance between the green oil-covered via and the pad should be greater than 0.1mm (4mil). Method: Open Same Net DRC, check DRC, and then close Same Net DRC.
101. The arrangement of the vias should not be too dense to avoid large-scale fractures of the power supply and the ground plane
102. The through-hole diameter for drilling is preferably no less than 1/10 of the plate thickness

103. Is the device deployment rate 100%? Is the conduction rate 100%? (If it does not reach 100%, it needs to be noted in the remarks.)
104. Has the Dangling line been adjusted to the minimum? The remaining Dangling lines have been confirmed one by one.
105. Have the process issues fed back by the Process department been carefully checked

106. For large areas of copper foil on the Top and bottom, unless there are special requirements, grid copper should be applied [use diagonal mesh for single plates and orthogonal mesh for backplates, with a line width of 0.3mm (12 mil) and a spacing of 0.5mm (20mil].
107. For component pads with large copper foil areas, they should be designed as patterned pads to avoid false soldering. When there is a current requirement, first consider widening the ribs of the flower pad, and then consider full connection

When large-scale copper distribution is carried out, it is advisable to avoid dead copper (isolated islands) without network connections as much as possible.

109. For large-area copper foil, it is also necessary to pay attention to whether there are illegal connections or unreported DRC

110. Are there sufficient test points for various power supplies and ground (at least one test point for every 2A current)?
111. It is confirmed that all networks without test points have been confirmed to be streamlined
112. Confirm that no test points have been set on the plugins that were not installed during production
113. Have the Test Via and Test Pin been fixed? (Applicable to the modified board where the test pin bed remains unchanged)

114. The Spacing Rule of Test via and Test pin should first be set to the recommended distance to check DRC. If DRC still exists, the minimum distance setting should then be used to check DRC
115. Open the constraint setting to the open state, update DRC, and check if there are any prohibited errors in DRC
116. Confirm that DRC has been adjusted to the minimum. For those that cannot eliminate DRC, confirm one by one.

117. Confirm that the PCB surface with surface mount components already has optical positioning symbols
118. Confirm that the optical positioning symbols are not embossed (silk-screened and copper foil routed).
119. The background of the optical positioning points must be the same. Confirm that the center of the optical points used on the entire board is ≥5mm away from the edge
120. Confirm that the optical positioning reference symbol of the entire board has been assigned coordinate values (it is recommended to place the optical positioning reference symbol in the form of a device), and it is an integer value in millimeters.

For ics with a pin center distance of less than 0.5mm and BGA devices with a center distance of less than 0.8mm (31 mil), optical positioning points should be set near the diagonal of the components